7.1.4. Legacy Interrupts
Legacy interrupts mimic the original PCI level-sensitive interrupts using virtual wire messages. The Intel® Arria® 10 or Intel® Cyclone® 10 GX signals legacy interrupts on the PCIe link using Message TLPs. The term, INTx, refers collectively to the four legacy interrupts, INTA#, INTB#, INTC# and INTD#. The Intel® Arria® 10 or Intel® Cyclone® 10 GX asserts app_int_sts to cause an Assert_INTx Message TLP to be generated and sent upstream. Deassertion of app_int_sts causes a Deassert_INTx Message TLP to be generated and sent upstream. To use legacy interrupts, you must clear the Interrupt Disable bit, which is bit 10 of the Command register. Then, turn off the MSI Enable bit.
The following figures illustrates interrupt timing for the legacy interface. The legacy interrupt handler asserts app_int_sts to instruct the Intel L-/H-Tile Avalon-ST for PCI Express IP to send a Assert_INTx message TLP.
The following figure illustrates the timing for deassertion of legacy interrupts. The legacy interrupt handler asserts app_int_sts causing the Intel L-/H-Tile Avalon-ST for PCI Express IP to send a Deassert_INTx message.
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