Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon® Streaming Interface for PCI Express* User Guide

ID 683647
Date 6/03/2021
Public
Document Table of Contents

Use the reset_status output of the Hard IP to drive the reset of your Application Layer logic.

After pin_perst or npor is released, the Hard IP reset controller deasserts reset_status. Your Application Layer logic can then come out of reset and become operational.

RX Transceiver Reset Sequence

The RX transceiver reset sequence includes the following steps:

  1. After rx_pll_locked is asserted, the LTSSM state machine transitions from the Detect.Quiet to the Detect.Active state.
  2. When the pipe_phystatus pulse is asserted and pipe_rxstatus[2:0] = 3, the receiver detect operation has completed.
  3. The LTSSM state machine transitions from the Detect.Active state to the Polling.Active state.
  4. The Hard IP for PCI Express asserts rx_digitalreset. The rx_digitalreset signal is deasserted after rx_signaldetect is stable for a minimum of 3 ms.
TX Transceiver Reset Sequence

The TX transceiver reset sequence includes the following steps:

  1. After npor is deasserted, the IP core deasserts the npor_serdes input to the TX transceiver.
  2. The SERDES reset controller waits for pll_locked to be stable for a minimum of 127 pld_clk cycles before deasserting tx_digitalreset.

For descriptions of the available reset signals, refer to Reset Signals, Status, and Link Training Signals.