Arria® 10 and Cyclone® 10 GX Avalon® Streaming Interface for PCI Express* User Guide

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ID 683647
Date 9/11/2024
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Document Table of Contents
Document Table of Contents x
1. Datasheet 2. Quick Start Guide 3. Arria® 10 or Cyclone® 10 GX Parameter Settings 4. Physical Layout 5. Interfaces and Signal Descriptions 6. Registers 7. Reset and Clocks 8. Interrupts 9. Error Handling 10. PCI Express Protocol Stack 11. Transaction Layer Protocol (TLP) Details 12. Throughput Optimization 13. Design Implementation 14. Additional Features 15. Hard IP Reconfiguration 16. Testbench and Design Example 17. Debugging A. Transaction Layer Packet (TLP) Header Formats B. Lane Initialization and Reversal C. Arria® 10 or Cyclone® 10 GX Avalon-ST Interface for PCIe Solutions User Guide Archive D. Document Revision History
1. Datasheet x
1.1. Arria® 10 or Cyclone® 10 GX Avalon-ST Interface for PCI Express* Datasheet 1.2. Release Information 1.3. Device Family Support 1.4. Configurations 1.5. Debug Features 1.6. IP Core Verification 1.7. Resource Utilization 1.8. Recommended Speed Grades 1.9. Creating a Design for PCI Express
1.1. Arria® 10 or Cyclone® 10 GX Avalon-ST Interface for PCI Express* Datasheet x
1.1.1. Arria® 10 or Cyclone® 10 GX Features
1.6. IP Core Verification x
1.6.1. Compatibility Testing Environment
2. Quick Start Guide x
2.1. Directory Structure 2.2. Design Components 2.3. Generating the Design 2.4. Simulating the Design 2.5. Compiling and Testing the Design in Hardware
3. Arria® 10 or Cyclone® 10 GX Parameter Settings x
3.1. Parameters 3.2. Arria® 10 or Cyclone® 10 GX Avalon-ST Settings 3.3. Base Address Register (BAR) and Expansion ROM Settings 3.4. Base and Limit Registers for Root Ports 3.5. Device Identification Registers 3.6. PCI Express and PCI Capabilities Parameters 3.7. Vendor Specific Extended Capability (VSEC) 3.8. Configuration, Debug, and Extension Options 3.9. PHY Characteristics 3.10. Example Designs
3.6. PCI Express and PCI Capabilities Parameters x
3.6.1. PCI Express and PCI Capabilities 3.6.2. Error Reporting 3.6.3. Link Capabilities 3.6.4. MSI and MSI-X Capabilities 3.6.5. Slot Capabilities 3.6.6. Power Management
4. Physical Layout x
4.1. Hard IP Block Placement In Cyclone® 10 GX Devices 4.2. Hard IP Block Placement In Arria® 10 Devices 4.3. Channel and Pin Placement for the Gen1, Gen2, and Gen3 Data Rates 4.4. Channel Placement and fPLL and ATX PLL Usage for the Gen3 Data Rate 4.5. PCI Express Gen3 Bank Usage Restrictions
5. Interfaces and Signal Descriptions x
5.1. Avalon‑ST RX Interface 5.2. Avalon-ST TX Interface 5.3. Clock Signals 5.4. Reset, Status, and Link Training Signals 5.5. ECRC Forwarding 5.6. Error Signals 5.7. Interrupts for Endpoints 5.8. Interrupts for Root Ports 5.9. Completion Side Band Signals 5.10. Parity Signals 5.11. LMI Signals 5.12. Transaction Layer Configuration Space Signals 5.13. Hard IP Reconfiguration Interface 5.14. Power Management Signals 5.15. Physical Layer Interface Signals
5.1. Avalon‑ST RX Interface x
5.1.1. Avalon-ST RX Component Specific Signals 5.1.2. Data Alignment and Timing for the 64‑Bit Avalon® -ST RX Interface 5.1.3. Data Alignment and Timing for the 128‑Bit Avalon‑ST RX Interface 5.1.4. Data Alignment and Timing for 256‑Bit Avalon‑ST RX Interface 5.1.5. Tradeoffs to Consider when Enabling Multiple Packets per Cycle
5.2. Avalon-ST TX Interface x
5.2.1. Avalon-ST Packets to PCI Express TLPs 5.2.2. Data Alignment and Timing for the 64‑Bit Avalon-ST TX Interface 5.2.3. Data Alignment and Timing for the 128‑Bit Avalon‑ST TX Interface 5.2.4. Data Alignment and Timing for the 256‑Bit Avalon‑ST TX Interface 5.2.5. Root Port Mode Configuration Requests
5.2.4. Data Alignment and Timing for the 256‑Bit Avalon‑ST TX Interface x
5.2.4.1. Single Packet Per Cycle 5.2.4.2. Multiple Packets per Cycle on the Avalon-ST TX 256-Bit Interface
5.12. Transaction Layer Configuration Space Signals x
5.12.1. Configuration Space Register Access Timing 5.12.2. Configuration Space Register Access
5.15. Physical Layer Interface Signals x
5.15.1. Serial Data Signals 5.15.2. PIPE Interface Signals 5.15.3. Test Signals 5.15.4. Arria® 10 Development Kit Conduit Interface
6. Registers x
6.1. Correspondence between Configuration Space Registers and the PCIe Specification 6.2. Type 0 Configuration Space Registers 6.3. Type 1 Configuration Space Registers 6.4. PCI Express Capability Structures 6.5. Intel-Defined VSEC Registers 6.6. Advanced Error Reporting Capability
6.5. Intel-Defined VSEC Registers x
6.5.1. CvP Registers
6.6. Advanced Error Reporting Capability x
6.6.1. Uncorrectable Internal Error Mask Register 6.6.2. Uncorrectable Internal Error Status Register 6.6.3. Correctable Internal Error Mask Register 6.6.4. Correctable Internal Error Status Register
7. Reset and Clocks x
7.1. Reset Sequence for Hard IP for PCI Express IP Core and Application Layer 7.2. Clocks
7.2. Clocks x
7.2.1. Clock Domains 7.2.2. Clock Summary
7.2.1. Clock Domains x
7.2.1.1. coreclkout_hip 7.2.1.2. pld_clk
8. Interrupts x
8.1. Interrupts for Endpoints 8.2. Interrupts for Root Ports
8.1. Interrupts for Endpoints x
8.1.1. MSI and Legacy Interrupts 8.1.2. MSI-X 8.1.3. Implementing MSI-X Interrupts 8.1.4. Legacy Interrupts
9. Error Handling x
9.1. Physical Layer Errors 9.2. Data Link Layer Errors 9.3. Transaction Layer Errors 9.4. Error Reporting and Data Poisoning 9.5. Uncorrectable and Correctable Error Status Bits
10. PCI Express Protocol Stack x
10.1. Top-Level Interfaces 10.2. Transaction Layer 10.3. Data Link Layer 10.4. Physical Layer
10.1. Top-Level Interfaces x
10.1.1. Avalon-ST Interface 10.1.2. Clocks and Reset 10.1.3. Local Management Interface (LMI Interface) 10.1.4. Hard IP Reconfiguration 10.1.5. Interrupts 10.1.6. PIPE
10.2. Transaction Layer x
10.2.1. Configuration Space
11. Transaction Layer Protocol (TLP) Details x
11.1. Supported Message Types 11.2. Transaction Layer Routing Rules 11.3. Receive Buffer Reordering
11.1. Supported Message Types x
11.1.1. INTX Messages 11.1.2. Power Management Messages 11.1.3. Error Signaling Messages 11.1.4. Locked Transaction Message 11.1.5. Slot Power Limit Message 11.1.6. Vendor-Defined Messages 11.1.7. Hot Plug Messages
11.3. Receive Buffer Reordering x
11.3.1. Using Relaxed Ordering
12. Throughput Optimization x
12.1. Throughput of Posted Writes 12.2. Throughput of Non-Posted Reads
13. Design Implementation x
13.1. Making Pin Assignments to Assign I/O Standard to Serial Data Pins 13.2. Recommended Reset Sequence to Avoid Link Training Issues 13.3. SDC Timing Constraints
14. Additional Features x
14.1. Configuration over Protocol (CvP) 14.2. Autonomous Mode 14.3. ECRC
14.2. Autonomous Mode x
14.2.1. Enabling Autonomous Mode 14.2.2. Enabling CvP Initialization
14.3. ECRC x
14.3.1. ECRC on the RX Path 14.3.2. ECRC on the TX Path
16. Testbench and Design Example x
16.1. Endpoint Testbench 16.2. Test Driver Module 16.3. Root Port BFM Overview 16.4. BFM Procedures and Functions
16.1. Endpoint Testbench x
16.1.1. Endpoint Testbench for SR-IOV
16.3. Root Port BFM Overview x
16.3.1. BFM Memory Map 16.3.2. Configuration Space Bus and Device Numbering 16.3.3. Configuration of Root Port and Endpoint 16.3.4. Issuing Read and Write Transactions to the Application Layer
16.4. BFM Procedures and Functions x
16.4.1. ebfm_barwr Procedure 16.4.2. ebfm_barwr_imm Procedure 16.4.3. ebfm_barrd_wait Procedure 16.4.4. ebfm_barrd_nowt Procedure 16.4.5. ebfm_cfgwr_imm_wait Procedure 16.4.6. ebfm_cfgwr_imm_nowt Procedure 16.4.7. ebfm_cfgrd_wait Procedure 16.4.8. ebfm_cfgrd_nowt Procedure 16.4.9. BFM Configuration Procedures 16.4.10. BFM Shared Memory Access Procedures 16.4.11. BFM Log and Message Procedures 16.4.12. Verilog HDL Formatting Functions
16.4.9. BFM Configuration Procedures x
16.4.9.1. ebfm_cfg_rp_ep Procedure 16.4.9.2. ebfm_cfg_decode_bar Procedure
16.4.10. BFM Shared Memory Access Procedures x
16.4.10.1. Shared Memory Constants 16.4.10.2. shmem_write Task 16.4.10.3. shmem_read Function 16.4.10.4. shmem_display Verilog HDL Function 16.4.10.5. shmem_fill Procedure 16.4.10.6. shmem_chk_ok Function
16.4.11. BFM Log and Message Procedures x
16.4.11.1. ebfm_display Verilog HDL Function 16.4.11.2. ebfm_log_stop_sim Verilog HDL Function 16.4.11.3. ebfm_log_set_suppressed_msg_mask Task 16.4.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task 16.4.11.5. ebfm_log_open Verilog HDL Function 16.4.11.6. ebfm_log_close Verilog HDL Function
16.4.12. Verilog HDL Formatting Functions x
16.4.12.1. himage1 16.4.12.2. himage2 16.4.12.3. himage4 16.4.12.4. himage8 16.4.12.5. himage16 16.4.12.6. dimage1 16.4.12.7. dimage2 16.4.12.8. dimage3 16.4.12.9. dimage4 16.4.12.10. dimage5 16.4.12.11. dimage6 16.4.12.12. dimage7
17. Debugging x
17.1. Simulation Fails To Progress Beyond Polling.Active State 17.2. Hardware Bring-Up Issues 17.3. Link Training 17.4. Creating a Signal Tap Debug File to Match Your Design Hierarchy 17.5. Use Third-Party PCIe Analyzer 17.6. BIOS Enumeration Issues
17.3. Link Training x
17.3.1. Link Hangs in L0 State
A. Transaction Layer Packet (TLP) Header Formats x
A.1. TLP Packet Formats without Data Payload A.2. TLP Packet Formats with Data Payload
D. Document Revision History x
D.1. Document Revision History of the Arria® 10 or Cyclone® 10 GX Avalon® Streaming (Avalon-ST) Interface for PCIe* Solutions User Guide
1. Datasheet
2. Quick Start Guide
3. Arria® 10 or Cyclone® 10 GX Parameter Settings
4. Physical Layout
5. Interfaces and Signal Descriptions
6. Registers
7. Reset and Clocks
8. Interrupts
9. Error Handling
10. PCI Express Protocol Stack
11. Transaction Layer Protocol (TLP) Details
12. Throughput Optimization
13. Design Implementation
14. Additional Features
15. Hard IP Reconfiguration
16. Testbench and Design Example
17. Debugging
A. Transaction Layer Packet (TLP) Header Formats
B. Lane Initialization and Reversal
C. Arria® 10 or Cyclone® 10 GX Avalon-ST Interface for PCIe Solutions User Guide Archive
D. Document Revision History

7.1. Reset Sequence for Hard IP for PCI Express IP Core and Application Layer

Use the reset_status output of the Hard IP to drive the reset of your Application Layer logic.

After pin_perst or npor is released, the Hard IP reset controller deasserts reset_status. Your Application Layer logic can then come out of reset and become operational.

Figure 82. RX Transceiver Reset Sequence

The RX transceiver reset sequence includes the following steps:

  1. After rx_pll_locked is asserted, the LTSSM state machine transitions from the Detect.Quiet to the Detect.Active state.
  2. When the pipe_phystatus pulse is asserted and pipe_rxstatus[2:0] = 3, the receiver detect operation has completed.
  3. The LTSSM state machine transitions from the Detect.Active state to the Polling.Active state.
  4. The Hard IP for PCI Express asserts rx_digitalreset. The rx_digitalreset signal is deasserted after rx_signaldetect is stable for a minimum of 3 ms.
Figure 83. TX Transceiver Reset Sequence

The TX transceiver reset sequence includes the following steps:

  1. After npor is deasserted, the IP core deasserts the npor_serdes input to the TX transceiver.
  2. The SERDES reset controller waits for pll_locked to be stable for a minimum of 127 pld_clk cycles before deasserting tx_digitalreset.

For descriptions of the available reset signals, refer to Reset Signals, Status, and Link Training Signals.

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