Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon® Streaming Interface for PCI Express* User Guide

ID 683647
Date 6/03/2021
Document Table of Contents

5.12. Power Management Signals

Table 40.  Power Management Signals






Power management turn off control register.

Root Port—When this signal is asserted, the Root Port sends the PME_turn_off message.

Endpoint—This signal is asserted to acknowledge the PME_turn_off message by sending pme_to_ack to the Root Port.



Power management turn off status register.

Root Port—This signal is asserted for 1 clock cycle when the Root Port receives the pme_turn_off acknowledge message.

Endpoint—This signal is asserted for 1 cycle when the Endpoint receives the PME_turn_off message from the Root Port.



Power Management Event. This signal is only available for Endpoints.

The Endpoint initiates a a power_management_event message (PM_PME) that is sent to the Root Port. If the Hard IP is in a low power state, the link exits from the low-power state to send the message. This signal is positive edge-sensitive.



Power Management Data.

This bus indicates power consumption of the component. This bus can only be implemented if all three bits of AUX_power (part of the Power Management Capabilities structure) are set to 0. This bus includes the following bits:

  • pm_data[9:2]: Data Register: This register maintains a value associated with the power consumed by the component. (Refer to the example below)
  • pm_data[1:0]: Data Scale: This register maintains the scale used to find the power consumed by a particular component and can include the following values:
  • 2b’00: unknown
  • 2b’01: 0.1 ×
  • 2b’10: 0.01 ×
  • 2b’11: 0.001 ×

For example, the two registers might have the following values:

  • pm_data[9:2]: b’1110010 = 114
  • pm_data[1:0]: b’10, which encodes a factor of 0.01

To find the maximum power consumed by this component, multiply the data value by the data Scale (114 × .01 = 1.14). 1.14 watts is the maximum power allocated to this component in the power state selected by the data_select field.



Power Management Auxiliary Power: This signal can be tied to 0 because the L2 power state is not supported.

Figure 38. Layout of Power Management Capabilities Register
Table 41.   Power Management Capabilities Register Field Descriptions





Data register

This field indicates in which power states a function can assert the PME# message.





When set to 1, indicates that the function would normally assert the PME# message independently of the state of the PME_en bit.



This field indicates the scaling factor when interpreting the value retrieved from the data register. This field is read-only.



This field indicates which data should be reported through the data register and the data_scale field.



1: indicates that the function can assert PME#0: indicates that the function cannot assert PME#





Specifies the power management state of the operating condition being described. The following encodings are defined:

  • 2b’00 D0
  • 2b’01 D1
  • 2b’10 D2
  • 2b’11 D3

A device returns 2b’11 in this field and Aux or PME Aux in the type register to specify the D3-Cold PM state. An encoding of 2b’11 along with any other type register value specifies the D3-Hot state.

Figure 39. pme_to_sr and pme_to_cr in an Endpoint IP core The following figure illustrates the behavior of pme_to_sr and pme_to_cr in an Endpoint. First, the Hard IP receives the PME_turn_off message which causes pme_to_sr to assert. Then, the Application Layer sends the PME_to_ack message to the Root Port by asserting pme_to_cr.

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