Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon® Streaming Interface for PCI Express* User Guide

ID 683647
Date 6/03/2021
Public
Document Table of Contents

15.4.9. BFM Configuration Procedures

The BFM configuration procedures are available in altpcietb_bfm_configure.v. These procedures support configuration of the Root Port and Endpoint Configuration Space registers.

All Verilog HDL arguments are type integer and are input‑only unless specified otherwise.

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