Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon® Streaming Interface for PCI Express* User Guide

ID 683647
Date 6/03/2021
Document Table of Contents

If you enable Multiple Packets Per Cycle under the Systems Settings heading, a TLP can start on a 128‑bit boundary. This mode supports multiple start of packet and end of packet signals in a single cycle when the Avalon‑ST interface is 256 bits wide. The following figure illustrates this mode for a 256-bit Avalon‑ST TX interface. In this figure tx_st_eop[0] and tx_st_sop[1] are asserted in the same cycle. Using this mode increases the complexity of the Application Layer logic but results in higher throughput, depending on the TX traffic. Refer to Tradeoffs to Consider when Enabling Multiple Packets per Cycle for an example of the bandwidth when Multiple Packets Per Cycle is enabled and disabled.

256-Bit Avalon-ST TX Interface with Multiple Packets Per Cycle