Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon® Streaming Interface for PCI Express* User Guide

ID 683647
Date 6/03/2021
Public
Document Table of Contents

2.3. Generating the Design

Figure 7. Procedure

Follow these steps to generate the design from the IP Parameter Editor:

  1. In the IP Catalog (Tools > IP Catalog) locate and select the Intel® Arria® 10/Cyclone 10 Hard IP for PCI Express.
  2. Starting with the Quartus® Prime Pro 16.1 software, the New IP Variation dialog box appears.
  3. Specify a top-level name and the folder for your custom IP variation, and the target device. Click OK
  4. On the IP Settings tabs, specify the parameters for your IP variation.
  5. On the Example Designs tab, the PIO design is available for your IP variation.
    Figure 8. Example Design Tab
  6. For Example Design Files, select the Simulation and Synthesis options.
  7. For Generated HDL Format, only Verilog is available.
  8. For Target Development Kit select the Intel® Arria® 10 FPGA Development Kit option.
    Note: Currently, you cannot select an Intel® Cyclone® 10 GX Development Kit when generating an example design.
  9. Click the Generate Example Design button. The software generates all files necessary to run simulations and hardware tests on the Intel® Arria® 10 FPGA Development Kit. Click Close when generation completes.
  10. Click Finish.
  11. The prompt, Recent changes have not been generated. Generate now?, allows you to create files for simulation and synthesis. Click No to continue to simulate the design example you just generated.

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