Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon® Streaming Interface for PCI Express* User Guide

ID 683647
Date 6/03/2021
Document Table of Contents

5.10.1. Configuration Space Register Access Timing

The tl_cfg_add and tl_cfg_ctl signals have multi-cycle paths. They update every eight coreclkout_hip cycles.

To ensure correct values are captured, your Application RTL must include code to force sampling to the middle of this window. The following example RTL captures the correct values of the tl_cfg busses in the case of an eight-cycle window. A generated strobe signal, cfgctl_addr_strobe, captures the address and data values by sampling them in the middle of the window.

// register LSB bit of tl_cfg_add
      always @(posedge coreclkout_hip)
      tl_cfg_add_reg <= tl_cfg_add[0];
      tl_cfg_add_reg2 <= tl_cfg_add_reg;
      // detect the address change to generate a strobe to sample the input 32-bit data
      always @(posedge coreclkout_hip)
      cfgctl_addr_change <= tl_cfg_add_reg2 != tl_cfg_add_reg; 
      cfgctl_addr_change2 <= cfgctl_addr_change; 
      cfgctl_addr_strobe <= cfgctl_addr_change2;
      // capture cfg ctl addr/data bus with the strobe
      always @(posedge coreclkout_hip)
      captured_cfg_addr_reg[3:0] <= tl_cfg_add[3:0];
      captured_cfg_data_reg[31:0] <= tl_cfg_ctl[31:0];
Note: Before Quartus® Prime version 16.0.1, the multi-cycle paths did not include proper timing constraints. If you use this interface, you must upgrade to 16.0.1 or later to ensure proper sampling of the tl_cfg_ctl bus.
Figure 34. Sample tl_cfg_ctl in the Middle of Eight-Cycle Window