Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon® Streaming Interface for PCI Express* User Guide

ID 683647
Date 6/03/2021
Document Table of Contents

If you enable Multiple Packets Per Cycle under the Systems Settings heading, a TLP can start on a 128‑bit boundary. This mode supports multiple start of packet and end of packet signals in a single cycle when the Avalon‑ST interface is 256 bits wide. It reduces the wasted bandwidth for small packets.

A comparison of the largest and smallest packet sizes illustrates this point. Large packets using the full 256 bits achieve the following throughput:

256/256*8 = 8 GBytes/sec

The smallest PCIe packet, such as a 3-dword memory read, uses 96 bits of the 256-bits bus and achieve the following throughput:

96/256*8 = 3 GBytes/sec

If you enable Multiple Packets Per Cycle, when a TLP ends in the upper 128 bits of the Avalon‑ST bus, a new TLP can start in the lower 128 bits Consequently, the bandwidth of small packets doubles:

96*2/256*8 = 6 GBytes/sec

This mode adds complexity to the Application Layer user decode logic. However, it could result in higher throughput.

256-Bit Avalon-ST RX Interface with Multiple Packets Per Cycle

The following figure illustrates this mode for a 256-bit Avalon‑ST RX interface. In this figure rx_st_eop[0] and rx_st_sop[1] are asserted in the same cycle.