Cyclone V Device Handbook: Volume 2: Transceivers

ID 683586
Date 10/24/2018
Public
Document Table of Contents

1.3.2.1.3. Word Aligner in Bit-Slip Mode

In bit-slip mode, the word aligner is controlled by the rx_bitslip bit of the pcs8g_rx_wa_control register. At every 0-1 transition of the rx_bitslip bit of the pcs8g_rx_wa_control register, the bit-slip circuitry slips one bit into the received data stream, effectively shifting the word boundary by one bit. Also in bit-slip mode, the word aligner pcs8g_rx_wa_status register bit for rx_patterndetect is driven high for one parallel clock cycle when the received data after bit-slipping matches the 16-bit word alignment pattern programmed.

To achieve word alignment, you can implement a bit-slip controller in the FPGA fabric that monitors the rx_parallel_data signal, the rx_patterndetect signal, or both, and controls them with the rx_bitslip signal.

Table 19.  Word Aligner in Bit-Slip Mode
PCS Mode PMA–PCS Interface Width (bits) Word Alignment Operation
Single Width 8
  1. At every rising edge to the rx_bitslip signal, the word aligner slips one bit into the received data.
  2. When bit-slipping shifts a complete round of the data bus width, the word boundary is back to the original boundary.
  3. Check the received data, rx_parallel_data after every bit slip operation whether the predefined word alignment pattern is visible in the new word boundary. When the word alignment pattern is visible in the new word boundary, the alignment process is completed and the bit-slip operation can be stopped.
10
Double Width 16
20
Note: For every bit slipped in the word aligner, the earliest bit received is lost.

For this example, consider that 8'b11110000 is received back-to-back and 16'b0000111100011110 is the predefined word alignment pattern. A rising edge on the rx_std_bitslip signal at time n + 1 slips a single bit 0 at the MSB position, forcing the rx_parallel_data to 8'b01111000. Another rising edge on the rx_std_bitslip signal at time n + 5 forces rx_parallel_data to 8'b00111100. Another rising edge on the rx_std_bitslip signal at time n + 9 forces rx_parallel_data to 8'b00011110. Another rising edge on the rx_std_bitslip signal at time n + 13 forces the rx_parallel_data to 8'b00001111. At this instance, rx_parallel_data in cycles n + 12 and n + 13 is 8'b00011110 and 8'b00001111, respectively, which matches the specified 16-bit alignment pattern 16'b0000111100011110.

Figure 28. Word Aligner Configured in Bit Slip Mode


Note: Bit slip operation can also be triggered by a 0 to 1 transition in the rx_bitslip register.