Cyclone V Device Handbook: Volume 2: Transceivers

ID 683586
Date 10/24/2018
Document Table of Contents

2.1. Input Reference Clocking

This section describes how the reference clock for the transmitter PLL and CDR is provided to generate the clocks required for transceiver operation.
Table 31.  Input Reference Clock Sources
Sources Transmitter PLL CDR Jitter Performance 6
Dedicated refclk pin Yes Yes 1
REFCLK network Yes Yes 2
Dual-purpose RX / refclk pin Yes Yes 3
Fractional PLL Yes Yes 4
Generic CLK pin No No 5
Core clock network (GCLK, RCLK, PCLK) No No 6
6 The lower number indicates better jitter performance.