Cyclone V Device Handbook: Volume 2: Transceivers

ID 683586
Date 10/24/2018
Document Table of Contents

1.3.2. Receiver PCS Datapath

The sub-blocks in the receiver PCS datapath are described in order from the word aligner to the receiver phase compensation FIFO block.

Table 16.  Blocks in the Receiver PCS Datapath
Block Functionality
Word Aligner
  • Searches for a predefined alignment pattern in the deserialized data to identify the correct boundary and restores the word boundary during link synchronization
  • Supports an alignment pattern length of 7, 8, 10, 16, 20, or 32 bits
  • Supports operation in four modes—manual alignment, bit-slip, automatic synchronization state machine, and deterministic latency state machine—in single- and double-width configurations
  • Supports the optional programmable run-length violation detection, polarity inversion, bit reversal, and byte reversal features
Rate Match FIFO
  • Compensates for small clock frequency differences of up to ±300 parts per million (ppm)—600 ppm total—between the upstream transmitter and the local receiver clocks by inserting or deleting skip symbols when necessary
  • Supports operation that is compliant to the clock rate compensation function in supported protocols
8B/10B Decoder
  • Receives 10-bit data and decodes the data into an 8-bit data and a 1-bit control identifier—in compliance with Clause 36 of the IEEE 802.3 specification
  • Supports operation in single- and double-width modes
Byte Deserializer
  • Halves the FPGA fabric–transceiver interface frequency at the receiver channel by doubling the receiver output datapath width
  • Allows the receiver channel to operate at higher data rates with the FPGA fabric–transceiver interface frequency that is within maximum limit
  • Supports operation in single- and double-width modes
Byte Ordering
  • Searches for a predefined pattern that must be ordered to the LSByte position in the parallel data going to the FPGA fabric when you enable the byte deserializer
Receiver Phase Compensation FIFO
  • Compensates for the phase difference between the low-speed parallel clock and the FPGA fabric interface clock when interfacing the receiver PCS with the FPGA fabric directly or with the PCIe hard IP block
  • Supports operation in phase compensation and registered modes