Cyclone V Device Handbook: Volume 2: Transceivers

ID 683586
Date 10/24/2018
Document Table of Contents

4.3.3. Transceiver Clocking and Channel Placement Guidelines in XAUI Configuration

Transceiver Clocking

Figure 85. Transceiver Clocking for XAUI ConfigurationOne of the two channel PLLs configured as a CMU PLL in a transceiver bank generates the transmitter serial and parallel clocks for the four XAUI channels. The x6 clock line carries the transmitter clocks to the PMA and PCS of each of the four channels.

Table 52.  Input Reference Clock Frequency and Interface Speed Specifications for XAUI Configurations
Input Reference Clock Frequency (MHz) FPGA Fabric-Transceiver Interface Width FPGA Fabric-Transceiver Interface Frequency (MHz)
156.25 16-bit data, 2-bit control 156.25

Transceiver Clocking Guidelines for Soft PCS Implementation

In the soft PCS implementation in the XAUI configuration, you must route xgmii_rx_clk to xgmii_tx_clk as shown in the following figure.

This method uses xgmii_rx_clk to compensate for the phase difference on the TX side.

Without this method, the tx_digitalreset signal may experience intermittent failure.

Figure 86. Transceiver Clocking for XAUI Soft PCS Implementation

Transceiver Channel Placement Guidelines

In the soft PCS implementation of the XAUI configuration, you can construct the four XAUI lanes at any channels within the two transceiver banks. However, Altera recommends you place the four channels contiguously to close timing more easily The channels may all be placed in one bank or they may span two banks. The following figure shows several possible channel placements when using the CMU PLL to drive the XAUI link.

Figure 87. Transceiver Channel Placement Guidelines in a XAUI Configuration The Quartus II software implements the XAUI PCS in soft logic. Each XAUI link requires a dedicated CMU PLL. A single CMU PLL cannot be shared among different XAUI links.