1. Transceiver Architecture in Cyclone V Devices
2. Transceiver Clocking in Cyclone V Devices
3. Transceiver Reset Control in Cyclone V Devices
4. Transceiver Protocol Configurations in Cyclone V Devices
5. Transceiver Custom Configurations in Cyclone V Devices
6. Transceiver Loopback Support
7. Dynamic Reconfiguration in Cyclone V Devices
1.3.2.1.1. Word Aligner Options and Behaviors
1.3.2.1.2. Word Aligner in Manual Alignment Mode
1.3.2.1.3. Word Aligner in Bit-Slip Mode
1.3.2.1.4. Word Aligner in Automatic Synchronization State Machine Mode
1.3.2.1.5. Word Aligner in Automatic Synchronization State Machine Mode with a 10-Bit PMA-PCS Interface Configuration
1.3.2.1.6. Word Aligner Operations in Deterministic Latency State Machine Mode
1.3.2.1.7. Programmable Run-Length Violation Detection
1.3.2.1.8. Receiver Polarity Inversion
1.3.2.1.9. Bit Reversal
1.3.2.1.10. Receiver Byte Reversal
3.1. PHY IP Embedded Reset Controller
3.2. User-Coded Reset Controller
3.3. Transceiver Reset Using Avalon Memory Map Registers
3.4. Clock Data Recovery in Manual Lock Mode
Resetting the Transceiver During Dynamic Reconfiguration
3.6. Transceiver Blocks Affected by the Reset and Powerdown Signals
3.7. Transceiver Power-Down
3.8. Document Revision History
3.2.1. User-Coded Reset Controller Signals
3.2.2. Resetting the Transmitter with the User-Coded Reset Controller During Device Power-Up
3.2.3. Resetting the Transmitter with the User-Coded Reset Controller During Device Operation
3.2.4. Resetting the Receiver with the User-Coded Reset Controller During Device Power-Up Configuration
3.2.5. Resetting the Receiver with the User-Coded Reset Controller During Device Operation
4.1.2.1. PIPE Interface
4.1.2.2. Transmitter Electrical Idle Generation
4.1.2.3. Power State Management
4.1.2.4. 8B/10B Encoder Usage for Compliance Pattern Transmission Support
4.1.2.5. Receiver Status
4.1.2.6. Receiver Detection
4.1.2.7. Clock Rate Compensation Up to ±300 ppm
4.1.2.8. PCIe Reverse Parallel Loopback
7.1. Dynamic Reconfiguration Features
7.2. Offset Cancellation
7.3. Transmitter Duty Cycle Distortion Calibration
7.4. PMA Analog Controls Reconfiguration
7.5. Dynamic Reconfiguration of Loopback Modes
7.6. Transceiver PLL Reconfiguration
7.7. Transceiver Channel Reconfiguration
7.8. Transceiver Interface Reconfiguration
7.9. Reduced .mif Reconfiguration
7.10. Unsupported Reconfiguration Modes
7.11. Document Revision History
4.3.3. Transceiver Clocking and Channel Placement Guidelines in XAUI Configuration
Transceiver Clocking
Figure 85. Transceiver Clocking for XAUI ConfigurationOne of the two channel PLLs configured as a CMU PLL in a transceiver bank generates the transmitter serial and parallel clocks for the four XAUI channels. The x6 clock line carries the transmitter clocks to the PMA and PCS of each of the four channels.
Input Reference Clock Frequency (MHz) | FPGA Fabric-Transceiver Interface Width | FPGA Fabric-Transceiver Interface Frequency (MHz) |
---|---|---|
156.25 | 16-bit data, 2-bit control | 156.25 |
Transceiver Clocking Guidelines for Soft PCS Implementation
In the soft PCS implementation in the XAUI configuration, you must route xgmii_rx_clk to xgmii_tx_clk as shown in the following figure.
This method uses xgmii_rx_clk to compensate for the phase difference on the TX side.
Without this method, the tx_digitalreset signal may experience intermittent failure.
Figure 86. Transceiver Clocking for XAUI Soft PCS Implementation
Transceiver Channel Placement Guidelines
In the soft PCS implementation of the XAUI configuration, you can construct the four XAUI lanes at any channels within the two transceiver banks. However, Altera recommends you place the four channels contiguously to close timing more easily The channels may all be placed in one bank or they may span two banks. The following figure shows several possible channel placements when using the CMU PLL to drive the XAUI link.
Figure 87. Transceiver Channel Placement Guidelines in a XAUI Configuration The Quartus II software implements the XAUI PCS in soft logic. Each XAUI link requires a dedicated CMU PLL. A single CMU PLL cannot be shared among different XAUI links.