Cyclone V Device Handbook: Volume 2: Transceivers

ID 683586
Date 10/24/2018
Document Table of Contents

1.2.2. Receiver PMA Datapath

There are three blocks in the receiver PMA datapath—the receiver buffer, channel PLL configured for clock data recovery (CDR) operation, and deserializer.

Table 6.  Functional Blocks in the Receiver PMA Datapath
Block Functionality
Receiver Buffer
  • Receives the serial data stream and feeds the stream to the channel PLL if you configure the channel PLL as a CDR
  • Supports the following features:
    • Programmable CTLE (Continuous Time Linear Equalization)
    • Programmable DC gain
    • Programmable VCM current strength
    • On-chip biasing for common-mode voltage (RX VCM )
    • I/O standard (1.5 V PCML, 2.5 V PCML, LVDS, LVPECL )
    • Differential OCT (85, 100, 120 and 150 Ω )
    • Signal detect
Channel PLL
  • Recovers the clock and serial data stream if you configure the channel PLL as a CDR.
  • Requires offset cancellation to correct the analog offset voltages.
  • If you do not use the channel PLL as a CDR, you can configure the channel PLL as a CMU PLL for clocking the transceivers.
  • Converts the incoming high-speed serial data from the receiver buffer to low-speed parallel data for the receiver PCS.
  • Receives serial data in LSB-to-MSB order.
  • Supports 8-, 10-, 16-, and 20-bit deserialization factors.
  • Supports the optional clock-slip feature for applications with stringent latency uncertainty requirement.