Cyclone V Device Handbook: Volume 2: Transceivers

ID 683586
Date 10/24/2018
Document Table of Contents Transmitter Buffer

Transmitter buffers support the programmable analog settings (differential output voltage and pre-emphasis), common-mode voltage (TX VCM), and OCT.

The transmitter buffer includes additional circuitry to improve integrity, such as the programmable differential output voltage (VOD), programmable three-tap pre-emphasis circuitry, internal termination circuitry, and PCIe receiver detect capability to support a PCIe configuration.

Modifying programmable values withing transmitter output buffers can be performed by a single reconfiguration controller for the entire FPGA, or multiple reconfiguration controllers if desired. Within each transceiver bank (three-transceiver channels), a maximum of one reconfiguration controller is allowed. There is only one slave interface to all PLLs and PMAs within each transceiver bank. Therefore, many transceiver banks can be connected to a single reconfiguration controller, but only one reconfiguration controller can be connected to the transceiver bank (three-transceiver channels).

Note: A maximum of one reconfiguration controller is allowed per transceiver bank.
Figure 9. Transmitter Buffer Block Diagram in Cyclone V Devices
Table 4.  Description of the Transmitter Buffer Features Features provided by the Pseudo Current Mode Logic (PCML) output buffer to the integrated circuitry.
Category Features Description
Improve Signal Integrity Programmable Differential Output Voltage (VOD) Controls the current mode drivers for signal amplitude to handle different trace lengths, various backplanes, and receiver requirements. The actual VOD level is a function of the current setting and the transmitter termination value.
Programmable Pre-Emphasis

Boosts the high-frequency components of the transmitted signal, which may be attenuated when propagating through the transmission medium. The physical transmission medium can be represented as a low-pass filter in the frequency domain. Variation in the signal frequency response that is caused by attenuation significantly increases the data-dependent jitter and other intersymbol interference (ISI) effects at the receiver end. Use the pre-emphasis feature to maximize the data opening at the far-end receiver.

Programmable Slew Rate Controls the rate of change for the signal transition.
Save Board Space and Cost On-Chip Biasing Establishes the required transmitter common-mode voltage (TX VCM) level at the transmitter output. The circuitry is available only if you enable OCT. When you disable OCT, you must implement off-chip biasing circuitry to establish the required TX VCM level.
Differential OCT

The termination resistance is adjusted by the calibration circuitry, which compensates for PVT.

You can disable OCT and use external termination. However, you must implement off-chip biasing circuitry to establish the required TX VCM level. TX VCM is tri-stated when you use external termination.

Reduce Power Programmable VCM Current Strength Controls the impedance of VCM. A higher impedance setting reduces current consumption from the on-chip biasing circuitry.
Protocol-Specific Function Transmitter Output Tri-State

Enables the transmitter differential pair voltages to be held constant at the same value determined by the TX VCM level with the transmitter in the high impedance state.

This feature is compliant with differential and common-mode voltage levels and operation time requirements for transmitter electrical idle, as specified in the PCI Express Base Specification 2.0 for Gen1 and Gen2 signaling rates.

Receiver Detect

Provides link partner detection capability at the transmitter end using an analog mechanism for the receiver detection sequence during link initialization in the Detect state of the PCIe Link Training and Status State Machine (LTSSM) states. The circuit detects if there is a receiver downstream by changing the transmitter common-mode voltage to create a step voltage and measuring the resulting voltage rise time.

For proper functionality, the series capacitor (AC-coupled link) and receiver termination values must comply with the PCI Express Base Specification 2.0 for Gen1 and Gen2 signaling rates. The circuit is clocked using fixedclk and requires an enabled transmitter OCT with the output tri-stated.