Cyclone V Device Handbook: Volume 2: Transceivers

ID 683586
Date 10/24/2018
Document Table of Contents PCIe Reverse Parallel Loopback

The PCIe reverse parallel loopback is only available in the PCIe functional configuration for the Gen1 data rate. The received serial data passes through the receiver CDR, deserializer, word aligner, and rate matching FIFO buffer. It is then looped back to the transmitter serializer and transmitted out through the transmitter buffer. The received data is also available to the FPGA fabric through the port.

PCIe reverse parallel loopback mode is compliant with PCIe specification 2.1.

Cyclone V devices provide the pipe_txdetectrx_loopback input signal to enable this loopback mode. If the pipe_txdetectrx_loopback signal is asserted in the P1 power state, receiver detection is performed. If the signal is asserted in the P0 power state, reverse parallel loopback is performed.

Note: The PCIe reverse parallel loopback is the only loopback option that is supported in PIPE configurations.
Figure 68. PIPE Reverse Parallel Loopback Mode Datapath