Cyclone V Device Handbook: Volume 2: Transceivers

ID 683586
Date 10/24/2018
Document Table of Contents Bit Reversal

By default, the receiver assumes a LSB-to-MSB transmission. If the transmission order is MSB-to-LSB, the receiver forwards the bit-flipped version of the parallel data to the FPGA fabric on rx_parallel_data. To reverse the bit order at the output of the word aligner to receive a MSB-to-LSB transmission, use the bit reversal feature at the receiver.

Table 25.  Bit Reversal Feature
Bit Reversal Option Received Bit Order
Single-Width Mode (8 or 10 bit) Double-Width Mode (16 or 20 bit)
Disabled (default) LSB to MSB LSB to MSB


For example:

8-bit—D[7:0] rewired to D[0:7]

10-bit—D[9:0] rewired to D[0:9]


For example:

16-bit—D[15:0] rewired to D[0:15]

20-bit—D[19:0] rewired to D[0:19]

Note: When receiving the MSB-to-LSB transmission, the word aligner receives the data in reverse order. The word alignment pattern must be reversed accordingly to match the MSB first incoming data ordering.

You can dynamically control the bit reversal feature to use the rx_bitreversal_enable register with the word aligner in bit-slip mode. When you dynamically enable the bit reversal feature in bit-slip mode, ignore the pattern detection function in the word aligner because the word alignment pattern cannot be dynamically reversed to match the MSB first incoming data order.