Cyclone V Device Handbook: Volume 2: Transceivers

ID 683586
Date 10/24/2018
Document Table of Contents Lock-to-Data Mode

During normal operation, the CDR must be in LTD mode to recover the clock from the incoming serial data. In LTD mode, the phase detector in the CDR tracks the incoming serial data at the receiver buffer. Depending on the phase difference between the incoming data and the CDR output clock, the phase detector controls the CDR charge pump that tunes the VCO.

Note: The PFD output is invalid in LTD mode. The rx_is_lockedtoref signal may toggle randomly and has no significance in LTD mode.

After switching to LTD mode, the rx_is_lockedtodata status signal is asserted. It can take a maximum of 1 ms for the CDR to lock to the incoming data and produce a stable recovered clock. The actual lock time depends on the transition density of the incoming data and the parts per million (ppm) difference between the receiver input reference clock and the upstream transmitter reference clock. The receiver PCS logic must be held in reset until the CDR produces a stable recovered clock.