Cyclone V Device Handbook: Volume 2: Transceivers

ID 683586
Date 10/24/2018
Document Table of Contents

1.2. PMA Architecture

The PMA includes the transmitter and receiver datapaths, clock multiplier unit (CMU) PLL—configured from the channel PLL—and the clock divider. The analog circuitry and differential on-chip termination (OCT) in the PMA requires the calibration block to compensate for process, voltage, and temperature variations (PVT).

Each transmitter channel has a clock divider. There are two types of clock dividers, depending on the channel location in a transceiver bank:

  • Channels 0, 2, 3, and 5—local clock divider
  • Channels 1 and 4—central clock divider

Using clocks from the clock lines and CMU PLL, the clock divider generates the parallel and serial clock sources for transmitter and optionally for the receiver PCS. The central clock divider can additionally feed the clock lines used to bond channels compared to the local clock divider.

Figure 8. PMA Block Diagram of a Transceiver Channel in Cyclone V Devices