Cyclone V Device Handbook: Volume 2: Transceivers

ID 683586
Date 10/24/2018
Document Table of Contents

7.1. Dynamic Reconfiguration Features

The following table lists the available dynamic reconfiguration features.
Table 62.  Reconfiguration Features
Reconfiguration Feature Description Affected Blocks
Offset Cancellation Counter offset variations due to process operation for the analog circuit. This feature is mandatory if you use receivers.


DCD Calibration Compensates for the duty cycle distortion caused by clock network skew. TX buffer and clock network skew
Analog Controls Reconfiguration Fine-tune signal integrity by adjusting the transmitter (TX) and receiver (RX) analog settings while bringing up a link. Analog circuit of TX and RX buffer
Loopback Modes Enable or disable Pre- and Post-CDR Reverse Serial Loopback dynamically. PMA
Data Rate Change Increase or decrease the data rate (/1, /2, /4, /8) for autonegotiation purposes such as CPRI and SATA/SAS applications TX Local clock dividers
Reconfigure the TX PLL settings for protocols with multi-data rate support such as CPRI TX PLL
Switch between multiple TX PLLs for multi-data rate support
  • TX PLL
  • Fractional PLL (Reconfigure the fPLL data rate with the ALTERA_PLL_RECONFIG megafunction.)
Channel reconfiguration—Reconfigure the RX CDR from one data rate to another data rate CDR
FPGA fabric - transceiver channel data width reconfiguration FPGA fabric - transceiver channel interface.