- 184.108.40.206.5. Word Aligner in Automatic Synchronization State Machine Mode with a 10-Bit PMA-PCS Interface Configuration
- 3.2.4. Resetting the Receiver with the User-Coded Reset Controller During Device Power-Up Configuration
4.1.3. PCIe Supported Configurations and Placement Guidelines
The following guidelines apply to all channel placements:
- The CMU PLL requires its own channel and must be placed on channel 1 or channel 4
- The PCIe channels must be contiguous within the transceiver bank
- Lane 0 of the PCIe must be placed on channel 0 or channel 5
In the following figures, channels shaded in blue provide the high-speed serial clock. Channels shaded in gray are data channels.
For PCIe Gen1 and Gen2, there are restrictions on the achievable x1 and x4 bonding configurations if you intend to use both top and bottom Hard IP blocks in the device.
|Top PCIe Hard IP||Bottom PCIe Hard IP||5CGXC4, 5CGXC5, 5CGTD5, 5CSXC5, 5CSTD5||5CGXC7, 5CGTD7, 5CSXC6, 5CSTD6||5CGXC9, 5CGTD9|
For full duplex transceiver channels, the following table lists the maximum number of data channels that can be enabled to ensure the channels meet the PCIe Gen2 Transmit Jitter Specification. Follow this recommendation when planning channel placement for PCIe Gen2 using Cyclone V GT or Cyclone V ST device variants.
|Device||Maximum Channels Utilization|
|5CGTD7F672, 5CGTD7F896, 5CGTD9F672, 5CSTD5F896, 5CSTD6F896||6|
Did you find the information on this page useful?