Cyclone V Device Handbook: Volume 2: Transceivers

ID 683586
Date 10/24/2018
Document Table of Contents

4.1.2. PCIe Supported Features

The PIPE configuration for the 2.5 Gbps (Gen1) and 5 Gbps (Gen2) data rates supports these features:

  • PCIe-compliant synchronization state machine
  • x1 and x4 link configurations
  • ±300 parts per million (ppm)—total 600 ppm—clock rate compensation
  • 8-bit FPGA fabric–transceiver interface
  • 16-bit FPGA fabric–transceiver interface
  • Transmitter buffer electrical idle
  • Receiver detection
  • 8B/10B encoder disparity control when transmitting compliance pattern
  • Power state management (Electrical Idle only)
  • Receiver status encoding