Cyclone V Device Handbook: Volume 2: Transceivers

ID 683586
Date 10/24/2018
Document Table of Contents Word Aligner

Parallel data at the input of the receiver PCS loses the word boundary of the upstream transmitter from the serial-to-parallel conversion in the deserializer. The word aligner receives parallel data from the deserializer and restores the word boundary based on a pre-defined alignment pattern that must be received during link synchronization.

The word aligner searches for a pre-defined alignment pattern in the deserialized data to identify the correct boundary and restores the word boundary during link synchronization. The alignment pattern is pre-defined for standard serial protocols according to the respective protocol specifications for achieving synchronization. For proprietary protocol implementations, you can specify a custom word alignment pattern specific to your application.

In addition to restoring the word boundary, the word aligner implements the following features:

  • Synchronization state machine
  • Programmable run length violation detection (for all transceiver configurations)
  • Receiver polarity inversion (for all transceiver configurations except PCIe)
  • Receiver bit reversal (for custom single- and double-width configurations only)
  • Receiver byte reversal (for custom double-width configuration only)

The word aligner operates in one of the following three modes:

  • Manual alignment
  • Automatic synchronization state machine
  • Bit-slip
  • Deterministic latency state machine

Except for bit-slip mode, after completing word alignment, the deserialized data is synchronized to have the word alignment pattern at the LSB portion of the aligned data.

When the 8B/10B encoder/decoder is enabled, the word aligner detects both positive and negative disparities of the alignment pattern. For example, if you specify a /K28.5/ (b’0011111010) pattern as the comma, rx_patterndetect is asserted if b’0011111010 or b’1100000101 is detected in the incoming data.