Cyclone V Device Handbook: Volume 2: Transceivers

ID 683586
Date 10/24/2018
Document Table of Contents Usage Restrictions on Specific Channels

Channels next to PCIe Hard IP block are not timing-optimized for the 6.144 Gbps CPRI data rate. Avoid placing the 6.144 Gbps CPRI channels in affected channels. The affected channels can still be used as a CMU to clock the CPRI channels.

Table 1.  Usage Restrictions on Specific Channels Across Device Variants
Channels Channel Bank Location Usage Restriction
Ch 1, Ch 2 GXB_L0
  • No 6.144 Gbps CPRI support
  • No support for PCS with phase compensation FIFO in registered mode
Ch 4, Ch 5 GXB_L11
Ch 1, Ch 2 GXB_L21

Cyclone V GX transceiver channels are comprised of a transmitter and receiver that can operate individually and simultaneously—providing a full-duplex physical layer implementation for high-speed serial interfacing.

The transmitter and receiver in a channel are structured into PMA and PCS sections:

  • PMA—converts serial data to parallel data and vice versa for connecting the FPGA to a serial transmission medium.
  • PCS—prepares the parallel data for transmission across a physical medium or restores the data to its original form using hard digital logic implementation.
1 Impacted only if the device has PCIe Hard IP block located next to this bank.