Cyclone V Device Handbook: Volume 2: Transceivers

ID 683586
Date 10/24/2018
Public
Document Table of Contents

2.3.2.1. Quartus II-Software Selected Transmitter Datapath Interface Clock

The Quartus II software automatically selects the appropriate clock from the FPGA fabric to clock the transmitter datapath interface.

The following figure shows the transmitter datapath interface of two transceiver non-bonded channels clocked by their respective transmitter PCS clocks, which are forwarded to the FPGA fabric.

Figure 50.  Transmitter Datapath Interface Clocking for Non-Bonded Channels


The following figure shows the transmitter datapath interface of three bonded channels clocked by the tx_clkout[0] clock. The tx_clkout[0] clock is derived from the central clock divider of channel 1 or 4 of the two transceiver banks.

Figure 51. Transmitter Datapath Interface Clocking for Three Bonded Channels