Cyclone V Device Handbook: Volume 2: Transceivers

ID 683586
Date 10/24/2018
Document Table of Contents

2.3. FPGA Fabric–Transceiver Interface Clocking

This section describes the clocking options available when the transceiver interfaces with the FPGA fabric.

The FPGA fabric-transceiver interface clocks consist of clock signals from the FPGA fabric to the transceiver blocks and clock signals from the transceiver blocks to the FPGA fabric. These clock resources use the clock networks in the FPGA core, including the global (GCLK), regional (RCLK), and periphery (PCLK) clock networks.

The FPGA fabric–transceiver interface clocks can be subdivided into the following three categories:

  • Input reference clocks—Can be an FPGA fabric–transceiver interface clock. This may occur when the FPGA fabric-transceiver interface clock is forwarded to the FPGA fabric, where it can then clock logic.
  • Transceiver datapath interface clocks—Used to transfer data, control, and status signals between the FPGA fabric and the transceiver channels. The transceiver channel forwards the tx_clkout signal to the FPGA fabric to clock the data and control signals into the transmitter. The transceiver channel also forwards the recovered rx_clkout clock (in configurations without the rate matcher) or the tx_clkout clock (in configurations with the rate matcher) to the FPGA fabric to clock the data and status signals from the receiver into the FPGA fabric.
  • Other transceiver clocks—The following transceiver clocks form a part of the FPGA fabric–transceiver interface clocks:
    • mgmt_clk—Avalon®-MM interface clock used for controlling the transceivers, dynamic reconfiguration, and calibration
    • fixed_clk—the 125 MHz fixed-rate clock used in the PCIe (PIPE) receiver detect circuitry
Table 39.  FPGA Fabric–Transceiver Interface Clocks
Clock Name Clock Description Interface Direction FPGA Fabric Clock Resource Utilization
tx_pll_refclk, rx_cdr_refclk Input reference clock used for clocking logic in the FPGA fabric Transceiver-to-FPGA fabric GCLK, RCLK, PCLK
tx_clkout, tx_pma_clkout Clock forwarded by the transceiver for clocking the transceiver datapath interface
rx_clkout, rx_pma_clkout Clock forwarded by the receiver for clocking the receiver datapath interface
tx_coreclkin User-selected clock for clocking the transmitter datapath interface FPGA fabric-to-transceiver
rx_coreclkin User-selected clock for clocking the receiver datapath interface
fixed_clk PCIe receiver detect clock
mgmt_clk 9 Avalon-MM interface management clock
Note: For more information about the GCLK, RCLK, and PCLK resources available in each device, refer to the Clock Networks and PLLs in Cyclone V Devices chapter.
9 The mgmt_clk is a free-running clock that is not derived from the transceiver blocks.