Cyclone V Device Handbook: Volume 2: Transceivers

ID 683586
Date 10/24/2018
Document Table of Contents Programmable Run-Length Violation Detection

The programmable run-length violation detection circuit resides in the word aligner block and detects if consecutive 1s or 0s in the received data exceed the user-specified threshold.

If the data stream exceeds the preset maximum number of consecutive 1s or 0s, the violation is signified by the assertion of the rx_rlv status bit.

Table 24.  Detection Capabilities of the Run-Length Violation Circuit
PCS Mode PMA–PCS Interface Width (bits) Run-Length Violation Detector Range
Minimum Maximum
Single Width 8 4 128
10 5 160
Double Width 16 8 512
20 10 640