Cyclone V Device Handbook: Volume 2: Transceivers

ID 683586
Date 10/24/2018
Document Table of Contents

6.4. Reverse Serial Loopback

You can use the reverse serial loopback option to debug with data through the rx_serial_data port, receiver CDR, and tx_serial_data port path.

You can enable reverse serial loopback through the reconfiguration controller.

Note: For further details, refer to the Altera Transceiver PHY IP Core User Guide.

In reverse serial loopback, the data is received through the rx_serial_data port, re-timed through the receiver CDR, and sent to the tx_serial_data port. The received data is also available to the FPGA logic. No dynamic pin control is available to select or deselect reverse serial loopback.

The transmitter buffer is the only active block in the transmitter channel. You can change the VOD and the pre-emphasis first post tap values on the transmitter buffer through the dynamic reconfiguration controller. Reverse serial loopback is often implemented when using a bit error rate tester (BERT) on the upstream transmitter.

Figure 111. Reverse Serial Loopback Datapath