Cyclone V Device Handbook: Volume 2: Transceivers

ID 683586
Date 10/24/2018
Document Table of Contents Receiver Detection

The PIPE interface block in Cyclone V transceivers provides an input signal (pipe_txdetectrx_loopback) for the receiver detect operation that is required by the PCIe protocol during the detect substate of the LTSSM.

When the pipe_txdetectrx_loopback signal is asserted in the P1 power state, the PCIe interface block sends a command signal to the transmitter buffer in that channel to initiate a receiver detect sequence. In the P1 power state, the transmitter buffer must always be in the electrical idle state.

After receiving this command signal, the receiver detect circuitry creates a step voltage at the output of the transmitter buffer. If an active receiver that complies with the PCIe input impedance requirements is present at the far end, the time constant of the step voltage on the trace is higher than if the receiver is not present. The receiver detect circuitry monitors the time constant of the step signal that is seen on the trace to determine if a receiver was detected. The receiver detect circuitry monitor requires a 125-MHz clock for operation that you must drive on the fixedclk port.

Note: For the receiver detect circuitry to function reliably, the AC-coupling capacitor on the serial link and the receiver termination values used in your system must be compliant with the PCIe Base Specification 2.1.

The PCI Express PHY (PIPE) IP core provides a 1-bit PHY status (pipe_phystatus) and a 3-bit receiver status signal (pipe_rxstatus[2:0]) to indicate whether a receiver was detected or not, in accordance to the PIPE specifications.