Cyclone V Device Handbook: Volume 2: Transceivers

ID 683586
Date 10/24/2018
Document Table of Contents Receiver Buffer

Table 7.  Cyclone Receiver Buffer Features
Category Features Description
Improve Signal Integrity Programmable Continuous Time Linear Equalization (CTLE) Boosts the high-frequency components of the received signal, which may be attenuated when propagating through the transmission medium. The physical transmission medium can be represented as a low-pass filter in the frequency domain. Variation in the signal frequency response that is caused by attenuation leads to data-dependent jitter and other ISI effects—causing incorrect sampling on the input data at the receiver. The amount of the high-frequency boost required at the receiver to overcome signal attenuation depends on the loss characteristics of the physical medium.
Programmable DC Gain Provides equal boost to the received signal across the frequency spectrum.
Save Board Space and Cost On-Chip Biasing Establishes the required receiver common-mode voltage (RX VCM) level at the receiver input. The circuitry is available only if you enable OCT. When you disable OCT, you must implement off-chip biasing circuitry to establish the required RX VCM level.
Differential OCT The termination resistance is adjusted by the calibration circuitry, which compensates for PVT. You can disable OCT and use external termination. However, you must implement off-chip biasing circuitry to establish the required RX VCM level. RX VCM is tri-stated when you use external termination.
Reduce Power Programmable VCM Current Strength Controls the impedance of VCM. A higher impedance setting reduces current consumption from the on-chip biasing circuitry.
Protocol-Specific Function Signal Detect

Senses if the signal level present at the receiver input is above or below the threshold voltage that you specified. The detection circuitry has a hysteresis response that asserts the status signal only when a number of data pulses exceeding the threshold voltage are detected and deasserts the status signal when the signal level below the threshold voltage is detected for a number of recovered parallel clock cycles. The circuitry requires the input data stream to be 8B/10B-coded.

Signal detect is compliant to the threshold voltage and detection time requirements for electrical idle detection conditions as specified in the PCI Express Base Specification 2.0 for Gen1 and Gen2 signaling rates. Signal detect is also compliant to SATA/SAS protocol up to 3 Gbps support.

You can AC-couple the receiver to a transmitter. In an AC-coupled link, the AC-coupling capacitor blocks the transmitter common-mode voltage. At the receiver end, the termination and biasing circuitry restores the common-mode voltage level that is required by the receiver.

Figure 13. AC-Coupled Link with a Cyclone V Receiver

The receiver buffers support the programmable analog settings (CTLE and DC gain), programmable common mode voltage (RX VCM), OCT, and signal detect function.

The receiver input buffer receives serial data from the high-speed differential receiver channel input pins and feeds the serial data to the channel PLL configured as a CDR unit.

Figure 14. Receiver Buffer Block Diagram in Cyclone V Devices

Modifying programmable values within receiver input buffers can be performed by a single reconfiguration controller for the entire FPGA, or multiple reconfiguration controllers if desired. Within each transceiver bank (three-transceiver channels) a maximum of one reconfiguration controller is allowed. There is only one slave interface to all PLLs and PMAs within each transceiver bank. Therefore, many transceiver banks can be connected to a single reconfiguration controller, but only one reconfiguration controller can be connected to the transceiver bank (three-transceiver channels).

Note: A maximum of one reconfiguration controller is allowed per transceiver bank.