Cyclone V Device Handbook: Volume 2: Transceivers

ID 683586
Date 10/24/2018
Document Table of Contents

2.3.1. Transceiver Datapath Interface Clocking

There are two types of design considerations for clock optimization when interfacing the transceiver datapath to the FPGA fabric:
  • PCS with FIFO in phase compensation mode – share clock network for identical channels
  • PCS with FIFO in registered mode or PMA direct mode – refer to AN 580: Achieving Timing Closure in Basic (PMA Direct) Functional Mode, for additional timing closure techniques between transceiver and FPGA fabric

The following sections describe design considerations for interfacing the PCS transmitter and PCS receiver datapath to the FPGA fabric with FIFO in phase compensation mode.