Cyclone V Device Handbook: Volume 2: Transceivers

ID 683586
Date 10/24/2018
Document Table of Contents Dedicated refclk Using the Reference Clock Network

Designs that use multiple channel PLLs with the same clock frequency can use the same dedicated refclk pin. Each dedicated refclk pin can drive any channel PLL (CMU PLL/CDR) and the fractional PLL through the reference clock network.

Input Reference Clock Sources for Transceiver Channels shows the input reference clock sources for six channel PLLs across two transceiver banks. For six transceiver channels, the total number of clock lines in the reference clock network is 2 (N = 6/3).