Cyclone V Device Handbook: Volume 2: Transceivers

ID 683586
Date 10/24/2018
Document Table of Contents

2.2. Internal Clocking

This section describes the clocking architecture internal to Cyclone V transceivers.

Different physical coding sublayer (PCS) configurations and channel bonding options result in various transceiver clock paths.

Note: The Quartus II software automatically performs the internal clock routing based on the transceiver configuration that you select.
The labels listed in the following table and figure mark the three sections of the transceiver internal clocking.
Table 32.  Internal Clocking Subsections
Label Scope Description
A Transmitter Clock Network Clock distribution from transmitter PLLs to channels
B Transmitter Clocking Clocking architecture within transmitter channel datapath
C Receiver Clocking Clocking architecture within receiver channel datapath
Figure 39. Internal Clocking