Cyclone V Device Handbook: Volume 2: Transceivers

ID 683586
Date 10/24/2018
Document Table of Contents

1.1.3. Transceiver Channel Architecture

Cyclone® V transceiver channels support the following interface methods with the FPGA fabric:

  • Directly—bypassing the PIPE interface for the PCIe interface and PCIe hard IP block
  • Through the PIPE interface and PCIe hard IP block—for hard IP implementation of the PCIe protocol stacks (PHY/MAC, data link layer, and transaction layer)
Figure 7. Transceiver Channel Block Diagram in Cyclone V Devices

You can bond multiple channels to implement a multilane link.