Cyclone V Device Handbook: Volume 2: Transceivers

ID 683586
Date 10/24/2018
Document Table of Contents

2.3.2. Transmitter Datapath Interface Clocking

The write side of the TX phase compensation FIFO makes up the transmitter datapath interface. The transmitter datapath interface clock clocks this interface.

The following figure shows the transmitter datapath interface clocking. The transmitter PCS forwards the following clocks to the FPGA fabric:

  • tx_clkout—for each transmitter channel in a non-bonded configuration
  • tx_clkout[0]—for all transmitter channels in a bonded configuration
Figure 49. Transmitter Datapath Interface Clocking for Transceivers

All configurations that use the PCS channel must have a 0 parts per million (ppm) difference between write and read clocks of the transmitter phase compensation FIFO.

Note: For more information about interface clocking for each configuration, refer to the Transceiver Custom Configuration in Cyclone V Devices and Transceiver Protocol Configurations in Cyclone V Devices chapters.

You can clock the transmitter datapath interface with one of the following options:

  • The Quartus II-selected transmitter datapath interface clock
  • The user-selected transmitter datapath interface clock
Note: To reduce GCLK, RCLK, and PCLK resource utilization in your design, you can select the user-selection option to share the transceiver datapath interface clocks.