Visible to Intel only — GUID: nik1409855425976
Ixiasoft
Visible to Intel only — GUID: nik1409855425976
Ixiasoft
5.1.1. Custom Configuration Channel Options
The supported interface width varies depending on the usage of the byte serializer/deserializer (SERDES), and the 8B/10B encoder or decoder. The byte serializer or deserializer is assumed to be enabled. Otherwise, the maximum data rate supported is half of the specified value.
The maximum supported data rate varies depending on the customization.
Data Configuration | PMA-PCS Interface Width | PCS-FPGA Fabric Interface Width | Maximum Data Rate for GX and SX (Mbps) | Maximum Data Rate for GT and ST (Mbps) | |
---|---|---|---|---|---|
8B/10B Enabled | 8B/10B Disabled | ||||
Single-width | 8 | — | 8 | 1,500 | 1,500 |
16 | 3,000 | 3,000 | |||
10 | 8 | 10 | 1,875 | 1,875 | |
16 | 20 | 3,125 | 3,750 | ||
Double-width | 16 | — | 16 | 2,621.44 | 2,621.44 |
32 15 | 3,125 | 6,144 | |||
20 | 16 | 20 | 3,125 | 3,276.8 | |
32 15 | 40 15 | 3,125 | 6,144 |
In all the supported configuration options of the channel, the transmitter bit-slip function is optional, where:
- The blocks shown as “Disabled” are not used but incur latency.
- The blocks shown as “Bypassed” are not used and do not incur any latency.
- The transmitter bit-slip is disabled.