Cyclone V Device Handbook: Volume 2: Transceivers

ID 683586
Date 10/24/2018
Document Table of Contents

2.1.1. Dedicated Reference Clock Pins

Cyclone V devices have one dedicated reference clock (refclk) pin for each bank of three transceiver channels.

The dedicated reference clock pins drive the channel PLL in channel 1 or 4 directly. This option provides the best quality of input reference clock to the transmitter PLL and CDR.

Note: For specifications about the input frequency supported by the refclk pins, refer to the Cyclone V Device Datasheet.

As shown in the following figure the dedicated refclk pin direct connection to the channel PLL (which can be configured either as a CMU PLL or CDR) is only available in channel 1 of a transceiver bank and channel 4 of the neighboring transceiver bank.

Input Reference Clock Sources for Transceiver Channels