Cyclone V Device Handbook: Volume 2: Transceivers

ID 683586
Date 10/24/2018
Document Table of Contents

2. Transceiver Clocking in Cyclone V Devices

This chapter provides information about the Cyclone® V transceiver clocking architecture. The chapter describes the clocks that are required for operation, internal clocking architecture, and clocking options when the transceiver interfaces with the FPGA fabric.
Figure 36. Transceiver Clocking Architecture Overview