Cyclone V Device Handbook: Volume 2: Transceivers

ID 683586
Date 10/24/2018
Document Table of Contents

1.1. Architecture Overview

Figure 1. Basic Layout of Transceivers in a Cyclone V DeviceThis figure represents a Cyclone V device with transceivers. Other Cyclone V devices may have a different floor plan than the one shown here.

The embedded high-speed clock networks in Cyclone V devices provide dedicated clocking connectivity for the transceivers. You can also use the fractional phase-locked loop (fPLL) between the PMA and PCS to clock the transceivers.

The embedded PCIe hard intellectual property (IP) of Cyclone V devices implements the following PCIe protocol stacks:

  • Physical interface/media access control (PHY/MAC) layer
  • Data link layer
  • Transaction layer

The embedded hard IP saves significant FPGA resources, reduces design risks, and reduces the time required to achieve timing closure. The hard IP complies with the PCIe Base Specification 2.0 for Gen1 and Gen2 signaling data rates.