Cyclone V Device Handbook: Volume 2: Transceivers

ID 683586
Date 10/24/2018
Document Table of Contents Byte Ordering in Double-Width Mode

Byte ordering is supported only when you enable the byte deserializer.

Table 29.  Byte Ordering Operation in Double-Width Mode
PMA–PCS Interface Width FPGA Fabric–Transceiver Interface Width 8B/10B Decoder Byte Ordering Pattern Length Pad Pattern Length
16 bits 32 bits Disabled 8 or 16 bits 8 bits
20 bits 32 bits Enabled 94 or 18 bits5 9 bits4
40 bits Disabled 10 or 20 bits 10 bits
Figure 34. Byte Ordering Operation Example in Double-Width ModeAn example of a byte ordering operation in double-width mode (16-bit PMA-PCS interface width) where A1A2 is the predefined byte ordering pattern and P is the predefined pad pattern.

4 The MSB of the 9-bit pattern represents the 1-bit control identifier of the 8B/10B-decoded data. The lower 8 bits represent the 8-bit decoded code.
5 The 18-bit pattern consists of two sets of 9-bit patterns, individually represented as in the previous note.