Cyclone V Device Handbook: Volume 2: Transceivers

ID 683586
Date 10/24/2018
Document Table of Contents

1. Transceiver Architecture in Cyclone V Devices

Describes the Cyclone® V transceiver architecture, clocking, channels, channel bonding, and transmitter and receiver channel datapaths.

Altera® 28-nm Cyclone® V devices provide transceivers with the lowest power requirement at 3.125 and 6.144 Gigabits per second (Gbps). These transceivers comply with a wide range of protocols and data rate standards; however, 6.144 Gbps support is limited to the common public radio interface (CPRI) protocol only.

Cyclone® V devices have up to 12 transceiver channels with serial data rates between 614 megabits per second (Mbps) and 6.144 Gbps and have backplane-capable transceiver support for PCI Express® (PCIe®) Base Specification 2.0 Gen1 and Gen2 up to x4 bonded channels.

Cyclone® V transceiver channels are full-duplex and clock data recovery (CDR)–based with physical coding sublayer (PCS) and physical medium attachment (PMA) layers.