Cyclone V Device Handbook: Volume 2: Transceivers

ID 683586
Date 10/24/2018
Document Table of Contents

2.2.2. Transmitter Clocking

Transmitter (TX) clocking refers to the clocking architecture that is internal to the TX channel of a transceiver.

As shown in the following figure, the clock divider provides the serial clock to the serializer, and the parallel clock to the serializer and TX PCS. When the byte serializer is not used, the parallel clock clocks all the blocks up to the read side of the TX phase compensation FIFO. For configurations with the byte serializer, the parallel clock is divided by a factor of two for the byte serializer and the read side of the TX phase compensation FIFO. The read side clock of the TX phase compensation FIFO is also forwarded to the FPGA fabric to interface the FPGA fabric with the transceiver.

Figure 42.  Clocking Architecture for Transmitter PCS and PMA Configuration
Table 35.  Clock Sources for All TX PCS Blocks
PCS Block Side Clock Source
TX Phase Compensation FIFO Write FPGA fabric write clock, driven either by tx_clkout or tx_coreclkin
Read Parallel clock (divided). Clock forwarded to FPGA fabric as tx_clkout
Byte Serializer Write Parallel clock (divided) either by factor of 1 (not enabled), or factor of 2 (enabled)
Read Parallel clock
8B/10B Encoder Parallel clock
TX Bit Slip Parallel clock