Cyclone V Device Handbook: Volume 2: Transceivers

ID 683586
Date 10/24/2018
Public
Document Table of Contents

1.1.1. Transceiver Banks

Cyclone® V transceivers are grouped in transceiver banks of three channels. Some Cyclone V devices support four or five transceiver channels.

Every transceiver bank is comprised of three channels (ch 0, ch 1, and ch 2, or ch 3, ch 4 , and ch 5). The Cyclone® V device family has a total of four transceiver banks (for the largest density family) namely, GXB_L0, GXB_L1, GXB_L2 and GXB_L3.

The location of the transceiver bank boundaries are important for clocking resources, bonding channels, and fitting.

In some package variations, the total transceiver count is reduced.
Figure 2. GX/GT Devices with Three or Five Transceiver Channels and One PCIe Hard IP BlockThe PCIe Hard IP block is located across Ch 1 and Ch 2 of banks GXB_L0.
Figure 3. GX/GT Devices with Four or Six Transceiver Channels and Two PCIe Hard IP BlocksThe PCIe Hard IP blocks are located across Ch 1 and Ch 2 of bank GXB_L0, and Ch 4 and Ch 5 of bank GXB_L1.


Figure 4. GX/GT/SX/ST Devices with Nine Transceiver Channels and Two PCIe Hard IP BlocksThe PCIe Hard IP blocks are located across Ch 1 and Ch 2 of bank GXB_L0, and Ch 1 and Ch 2 of bank GXB_L2.


Figure 5. GX/GT Devices with 12 Transceiver Channels and Two PCIe Hard IP BlocksThe PCIe Hard IP blocks are located across Ch 1 and Ch 2 of bank GXB_L0, and Ch 1 and Ch 2 of bank GXB_L2.


Figure 6. SX Device with Six Transceiver Channels and One or Two PCIe Hard IP BlocksThe PCIe Hard IP blocks are located across Ch 1 and Ch 2 of bank GXB_L0, and Ch 4 and Ch 5 of bank GXB_L1.