Cyclone V Device Handbook: Volume 2: Transceivers

ID 683586
Date 10/24/2018
Document Table of Contents

2.3.3. Receiver Datapath Interface Clock

The read side of the RX phase compensation FIFO makes up the 6-Gbps receiver datapath interface. The receiver datapath interface clock clocks this interface.

The receiver PCS forwards the following clocks to the FPGA fabric:

  • rx_clkout—for each receiver channel in a non-bonded configuration when you do not use a rate matcher
  • tx_clkout—for each receiver channel in a non-bonded configuration when you use a rate matcher
  • single rx_clkout[0]—for all receiver channels in a bonded configuration
Figure 52. Receiver Datapath Interface Clocking

All configurations that use the PCS channel must have a 0 ppm difference between the receiver datapath interface clock and the read side clock of the RX phase compensation FIFO.

Note: For more information about interface clocking for each configuration, refer to the Transceiver Custom Configuration in Cyclone V Devices and Transceiver Protocol Configurations in Cyclone V Devices chapters.

You can clock the receiver datapath interface with one of the following options:

  • The Quartus II-selected receiver datapath interface clock
  • The user-selected receiver datapath interface clock
Note: To reduce GCLK, RCLK, and PCLK resource utilization in your design, you can select the user-selection option to share the transceiver datapath interface clocks.