Cyclone V Device Handbook: Volume 2: Transceivers

ID 683586
Date 10/24/2018
Document Table of Contents

1.3. PCS Architecture

Figure 21. PCS Block Diagram of a Transceiver Channel in a Cyclone V DeviceThe serial and parallel clocks are sourced from the clock divider.

The transceiver channel PCS datapath is categorized into two configurations—single-width and double-width, based on the transceiver channel PMA-PCS width (or serialization/deserialization factor).

Table 10.  PCS Datapath Configurations
Parameters Single-Width Double-Width
PMA–PCS Interface Width 8 or 10 bit 16 or 20 bit
FPGA Fabric–Transceiver Interface Width

8 or 10 bit

16 or 20 bit2

16 or 20 bit

32 or 40 bit2

2 The byte serializer and deserializer are enabled.