JESD204B Intel® FPGA IP User Guide

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ID 683442
Date 5/18/2022
Public
Document Table of Contents

4.1.2. TX PHY Layer

The 8B/10B encoder encodes the data before transmitting them through the serial line. The 8B/10B encoding has sufficient bit transition density (3-8 transitions per 10-bit symbol) to allow clock recovery by the receiver. The control characters in this scheme allow the receiver to:
  • synchronize to 10-bit boundary.
  • insert special character to mark the start and end of frames and start and end of multiframes.
  • detect single bit errors.

The JESD204B IP core supports transmission order from MSB first as well as LSB first. For MSB first transmission, the serialization of the left-most bit of 8B/10B code group (bit "a") is transmitted first.

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