JESD204B Intel® FPGA IP User Guide

ID 683442
Date 8/18/2022
Public
Document Table of Contents

4.3.5. Link Startup Sequence

Set the run-time LMF configuration when the txlink_rst_n or rxlink_rst_n signals are asserted. Upon txlink_rst_n or rxlink_rst_n deassertion, the JESD204B IP core begins operation. The following sections describe the detailed operation for each subclass mode.

TX (Subclass 0)

Upon reset deassertion, the JESD204B TX IP core is in CGS phase. SYNC_N deassertion from the converter device enables the JESD204B TX IP core to exit CGS phase and enter ILAS phase (if csr_lane_sync_en = 1) or User Data phase (if csr_lane_sync_en = 0).

TX (Subclass 1)

Upon reset deassertion, the JESD204B TX IP core is in CGS phase. SYNC_N deassertion from the converter device enables the JESD204B TX IP core to exit CGS phase. The IP core ensures that at least one SYSREF rising edge is sampled before exiting CGS phase and entering ILAS phase. This is to prevent a race condition where the SYNC_N is deasserted before SYSREF is sampled. SYSREF sampling is crucial to ensure deterministic latency in the JESD204B Subclass 1 system.

TX (Subclass 2)

Similar to Subclass 1 mode, the JESD204B TX IP core is in CGS phase upon reset deassertion. The LMFC alignment between the converter and IP core starts after SYNC_N deassertion. The JESD204B TX IP core detects the deassertion of SYNC_N and compares the timing to its own LMFC. The required adjustment in the link clock domain is updated in the register map. You need to update the final phase adjustment value in the registers for it to transfer the value to the converter during the ILAS phase. The DAC adjusts the LMFC phase and acknowledge the phase change with an error report. This error report contains the new DAC LMFC phase information, which allows the loop to iterate until the phase between them is aligned.

RX (Subclass 0)

The JESD204B RX IP core drives and holds SYNC_N (dev_sync_n signal) low when it is in reset. Upon reset deassertion, the JESD204B RX IP core checks if there is sufficient /K/ character to move its state machine out of synchronization request. Once sufficient /K/ character is detected, the IP core deasserts SYNC_N.

RX (Subclass 1)

The JESD204B RX IP core drives and holds the SYNC_N (dev_sync_n signal) low when it is in reset. Upon reset deassertion, the JESD204B RX IP core checks if there is sufficient /K/ character to move its state machine out of synchronization request. The IP core also ensures that at least one SYSREF rising edge is sampled before deasserting SYNC_N. This is to prevent a race condition where the SYNC_N is deasserted based on internal free-running LMFC count instead of the updated LMFC count after SYSREF is sampled.

RX (Subclass 2)

The JESD204B RX IP core behaves the same as in Subclass 1 mode. In this mode, the logic device is always the master timing reference. Upon SYNC_N deassertion, the ADC adjusts the LMFC timing to match the IP core.

Did you find the information on this page useful?

Characters remaining:

Feedback Message