JESD204B Intel® FPGA IP User Guide

ID 683442
Date 5/05/2023

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Document Table of Contents

6.1. Clocking Scheme

To verifying the clocking scheme, follow these steps:

  1. Check that the frame and link clock frequency settings are correct in the PLL Intel® FPGA IP or IOPLL Intel® FPGA IP.
  2. Check the device clock frequency at the FPGA and converter.
  3. For Subclass 1, check the SYSREF pulse frequency.
  4. Check the management clock frequency. For the design examples using Arria V, Cyclone V, and Stratix V devices, this frequency is 100 MHz.