JESD204B Intel® FPGA IP User Guide

ID 683442
Date 5/18/2022
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4.5.2. ADC–FPGA Subsystem Reset Sequence

Figure 22. ADC–FPGA Subsystem Reset Sequence Timing Diagram

The recommended ADC – FPGA subsystem bring-up sequence:

  1. Provide a free-running and stable reference clock to the converter and FPGA in the JESD204B subsystem. The reference clock for the converter is the device clock. Intel® recommends four reference clocks for the FPGA.
    1. The first reference clock is the calibration clock for the transceiver.
      • For Intel® Stratix® 10 devices, this is the clock at the OSC_CLK_1 pin for the calibration engine.
      • For Intel® Arria® 10 and Intel® Cyclone® 10 GX devices, this is the clock at the CLKUSR pin for the calibration engine.
      • For Arria® V, Cyclone® V, and Stratix® V devices, this is the clock for the transceiver reconfiguration controller.
    2. The second reference clock is the management clock for the transceiver reconfiguration interface and the JESD204B IP core Avalon® memory-mapped interface.
      • If the dynamic reconfiguration option is enabled for Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices, this reference clock is connected to the reconfig_clk input port of the JESD204B IP core.
    3. The third reference clock is the transceiver reference clock.
      • For Intel® Stratix® 10, you must provide the reference clock at the transceiver dedicated reference clock input pin.
      • For Intel® Arria® 10, Intel® Cyclone® 10 GX, Arria® V, Cyclone® V, and Stratix® V devices, this clock is also used as the reference clock for the core PLL (IOPLL Intel® FPGA IP core for Intel® Arria® 10 and Intel® Cyclone® 10 GX devices; and PLL Intel® FPGA IP core for Arria® V, Cyclone® V, and Stratix® V devices) if you share the device clock and the transceiver reference clock (refer to Figure 20).
    4. The fourth reference clock is the core PLL reference clock (device clock).
      • For Intel® Stratix® 10, you must provide the reference clock at the dedicated reference clock input pin at the IO bank.
      • For Intel® Arria® 10, Intel® Cyclone® 10 GX, Arria® V, Cyclone® V, and Stratix® V devices, this is the reference clock for the core PLL (IOPLL Intel® FPGA IP core for Intel® Arria® 10 and Intel® Cyclone® 10 GX devices; and PLL Intel® FPGA IP core for Arria® V, Cyclone® V, and Stratix® V devices) if you do not share the device clock and the transceiver reference clock (refer to Figure 20).
  2. Configure the FPGA. Hold the RX transceiver channel in reset.
    • For Intel® Arria® 10 and Intel® Cyclone® 10 GX devices, if the reference clock is not available for the transceiver CDR before the FPGA is configured, you need to hold the RX transceiver channels in reset and perform user calibration for the RX transceiver channels after the reference clock is stable. For more information about user calibration for the transceiver channels, refer to the Calibration chapter in the Intel® Arria® 10 or Intel® Cyclone® 10 GX Transceiver PHY User Guides.
  3. You can program the ADC through its SPI interface before or after configuring the FPGA. Ensure that the ADC PLL is locked before you proceed to the next step.
  4. Ensure that the FPGA device clock core PLL is locked to the reference clock.
  5. Deassert the FPGA RX transceiver channel reset. Do this by deasserting the reset input pin of the Transceiver PHY Reset Controller.
  6. Once the transceiver is out of reset (the rx_ready signal from the Intel® FPGA Transceiver PHY Reset Controller is asserted), deassert the Avalon® memory-mapped interface reset for the IP core. At the configuration phase, the subsystem can program the JESD204B IP core if the default IP core register settings need to change.
  7. Deassert both the link reset for the IP core and the frame reset for the transport layer.
  8. For subclass 1, if the continuous SYSREF pulses from the clock generator are present when the RX link reset is deasserted, the ADC-RX link initializes. If the SYSREF pulse is not present, trigger the clock generator to provide a SYSREF pulse to initialize the link. For subclass 0, the link initializes after the ADC is programmed and the RX link reset is deasserted.

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