JESD204B Intel® FPGA IP User Guide

ID 683442
Date 8/18/2022
Public
Document Table of Contents

6.6.1. Removing Irrelevant Signals and Adding E-Tile PHY Signals

The PHY signals for E-tile designs are different from the L-tile and H-tile designs. For E-tile designs, remove the irrelevant L-tile and H-tile signals from the Signal Tap Logic Analyzer and add the E-tile PHY signals.
  1. Remove the following signals from the rx_phy and tx_phy instances:
    • rx_phy
      • rx_analogreset
      • rx_digitalreset
      • rx_cal_busy
      • rx_seriallpbken
    • tx_phy
      • pll_locked
      • tx_analogreset
      • tx_digitalreset
      • tx_cal_busy
  2. In the rx_phy and tx_phy instances, use the node finder in the Signal Tap Logic Analyzer to add the following signals:
    • rx_phy

      *|inst_phy|inst_xcvr_rx_pma_ready_rx_pma_ready[L-1:0]

      *|inst_phy|inst_xcvr_rx_ready_rx_ready[L-1:0]

    • tx_phy

      *|inst_phy|inst_xcvr_tx_pma_ready_tx_pma_ready[L-1:0]

      *|inst_phy|inst_xcvr_tx_ready_tx_ready[L-1:0]]

    Note: L = number of lanes

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