JESD204B Intel® FPGA IP User Guide

ID 683442
Date 5/05/2023

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3.8.2. Pin Assignments

Set the pin assignments before you compile to provide direction to the Intel® Quartus® Prime software Fitter tool. You must also specify the signals that should be assigned to device I/O pins.
You can create virtual pins to avoid making specific pin assignments for top-level signals. This is useful when you want to perform compilation, but are not ready to map the design to hardware. Intel® recommends that you create virtual pins for all unused top-level signals to improve timing closure.
Note: Do not create virtual pins for the clock or reset signals.

For Intel Agilex® 7 and Intel® Stratix® 10 E-tile devices, use the E-Tile Channel Placement Tool to get a valid pinout. Specify the transceiver mode as PMA direct - NRZ.